Papers in international journals

[2024] J. Vieira, N. Roma, G. Falcao, P. Tomas, “NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators from Caches to DRAM”, IEEE Access, 2024.
[2023] J. Vieira, N. Roma, G. Falcao, P. Tomas, “gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation”, Computer Architecture Letters (CAL), 2023.
[2021] J. Vieira, N. Roma, G. Falcao, P. Tomas, “A Compute Cache System for Signal Processing Applications”, Journal of Signal Processing Systems (JSPS) 2020.
[2019] J. Vieira, R. P. Duarte, H. C. Neto, “kNN-STUFF: kNN STreaming Unit for Fpgas”, IEEE Access.

Papers in international conferences

[2022] J. Vieira, N. Roma, G. Falcao, and P. Tomás, “gem5-ndp: Near-Data Processing Architecture Simulation From Low-Level Caches to DRAM”, on International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), November 2022, Bordeaux, France.
[2020] J. Vieira, N. Roma, G. Falcao, P. Tomás, “Processing Convolutional Neural Networks on Cache”, on 45th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2020, Barcelona, Spain.
[2019] J. Vieira, E. Giacomin, Y. Mahmood Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza and P.-E. Gaillardon, “A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories”, on 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2019, Cusco, Peru.
[2018] J. Vieira, P. Ienne, N. Roma, P. Tomás and G. Falcao, “Exploiting Compute Caches for Memory Bound Vector Operations”, on International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), September 2018, Lyon, France.

[2020] J. Vieira, “Playing BlokusDuo in a ZYNQ Device: A Quest for an Efficient Algorithm”, on XVI Jornadas sobre Sistemas Reconfiguráveis (REC’2020), February 2020, Lisbon Portugal.

[2020] J. Vieira, E. Giacomin, Y. Mahmood Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza and P.-E. Gaillardon, “Accelerating Inference on Binary Neural Networks with Digital RRAM Processing“, VLSI-SoC: EDA the New Technology Enabler, Springer, 2020.

[2022] P.-E. Gaillardon, E. Giacomin, J. Vieira, “Digital RRAM-Based Convolutional Block”, United States patent US11450385B2. September 20, 2022.

[2018] Exploiting Processing Near Cache for Memory Bound Vector Operations
- Report
- Extended Abstract

[2024] Accelerating Memory-Bound Applications with Near-Data Processing: From Architectural Design to Full-System Simulation
- Report
- Extended Abstract