joaovieira

It is an enormous pleasure to share this achievement: my first-ever US patent on a Digital RRAM-Based Convolutional Block. I especially thank Professor Pierre-Emmanuel Gaillardon and Dr. Edouard Giacomin.

My paper titled “NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators from Caches to DRAM” was accepted in IEEE Access. Abstract: The accurate simulation and performance assessment of Near-Data Accelerators (NDAccs) is a complex challenge as it must consider the operation of the entire processing system, the impact of the Operating Read more…

My paper titled “gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation” was accepted in Computer Architecture Letters (CAL) 2023. Abstract: Attaining the performance and efficiency levels required by modern applications often requires the use of application-specific accelerators. However, writing synthesizable Register-Transfer Level code for such accelerators is a complex, Read more…

My paper titled “gem5-ndp: Near-Data Processing Architecture Simulation From Low-Level Caches to DRAM” was accepted in SBAC-PAD 2022, to be held in Bordeaux, from November 2nd to November 4th. Abstract: Unlike standard accelerators, the performance of Near-Data Processing (NDP) devices highly depends on the operation of the surrounding system, namely, Read more…

My paper titled “A Compute Cache for Signal Processing Applications” was accepted in the Journal of Signal Processing Systems (JSPS) 2020. Abstract: Nowadays, processing systems are constrained by the low efficiency of their memory subsystems. Although memories evolved into faster and more efficient devices through the years, they were still Read more…

I am proud to announce that we were the winners of the IEEE Access’ 2019 Best Multimedia Award (Part 2) with a video about our paper “kNN-STUFF: kNN STreaming Unit for Fpgas”. Check out the video here.

Following the article that I have published last year in VLSI-SoC entitled “A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories”, I am proud to announce that an extended version of that same article was published as a chapter of a book containing revised and extended Read more…

My paper titled “Processing Convolutional Neural Networks on Cache” was accepted in ICASSP 2020 to be held in Barcelona, Spain, from May 4th to May 8th. Abstract: With the advent of Big Data application domains, several Machine Learning signal-processing algorithms, such as Convolutional Neural Networks, are required to process progressively Read more…

My paper titled “Playing BlokusDuo in a ZYNQ Device: A Quest for an Efficient Algorithm” was accepted in REC’2020 to be held in Lisbon, Portugal, from February 10th to February 11th. This paper was written in the context of the BlokusDuo contest that will take place during the conference. Abstract: Read more…