{"id":501,"date":"2019-06-23T10:08:42","date_gmt":"2019-06-23T10:08:42","guid":{"rendered":"https:\/\/v2.joaomiguelvieira.com\/~joaovieira\/site\/?p=501"},"modified":"2019-12-07T10:56:42","modified_gmt":"2019-12-07T10:56:42","slug":"artigo-aceite-na-conferencia-vlsi-soc19","status":"publish","type":"post","link":"https:\/\/v2.joaomiguelvieira.com\/~joaovieira\/site\/pt\/2019\/06\/23\/artigo-aceite-na-conferencia-vlsi-soc19\/","title":{"rendered":"Artigo aceite na confer\u00eancia VLSI-SoC’19"},"content":{"rendered":"\n

O meu artigo designado “A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories”<\/em> <\/a>foi aceite na confer\u00eancia VLSI-SoC, que ter\u00e1 lugar em Cuzco, no Per\u00fa, de 6 a 9 de outubro.<\/p>\n\n\n\n

Sum\u00e1rio (apenas em ingl\u00eas):<\/strong><\/p>\n\n\n\n

The need for executing complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. The situation has led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the weights (and possibly the data being operated) using only one bit. Because approximately 90% of the operations executed by CNNs and BNNs are convolutions, a significant part of the memory transfers consists of fetching the convolutional kernels. Such kernels are usually small (e.g., 3\u00d73 operands), and particularly in BNNs redundancy is expected. Therefore, equal kernels can be mapped to the same memory addresses, requiring significantly less memory to store them. In this context, this paper presents a custom Binary Dot Product Engine (BDPE) for BNNs that exploits the features of Resistive Random Access Memory (ReRAM). This new engine allows accelerating the execution of the inference phase of BNNs. The novel BDPE locally stores the most used binary weights and performs binary convolution using computing capabilities enabled by the ReRAM. The system-level gem5 architectural simulator was used together with a C-based ML framework to evaluate the system’s performance and obtain power results. Results show that this novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area, when integrated with a 28 nm Fully Depleted Silicon On Insulator ARMv8 in-order core, in comparison to a fully-optimized baseline of YoloV3 XNOR-Net running in a unmodified CPU.<\/p>\n\n\n\n

\"\"<\/figure>\n","protected":false},"excerpt":{"rendered":"

O meu artigo designado “A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories” foi aceite na confer\u00eancia VLSI-SoC, que ter\u00e1 lugar em Cuzco, no Per\u00fa, de 6 a 9 de outubro. Sum\u00e1rio (apenas em ingl\u00eas): The need for executing complex Machine Learning (ML) algorithms, such as […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ngg_post_thumbnail":0,"footnotes":""},"categories":[149],"tags":[],"class_list":["post-501","post","type-post","status-publish","format-standard","hentry","category-investigacao"],"yoast_head":"\nArtigo aceite na confer\u00eancia VLSI-SoC'19 - Jo\u00e3o Vieira<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/v2.joaomiguelvieira.com\/~joaovieira\/site\/pt\/2019\/06\/23\/artigo-aceite-na-conferencia-vlsi-soc19\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Artigo aceite na confer\u00eancia VLSI-SoC'19 - Jo\u00e3o Vieira\" \/>\n<meta property=\"og:description\" content=\"O meu artigo designado “A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories” foi aceite na confer\u00eancia VLSI-SoC, que ter\u00e1 lugar em Cuzco, no Per\u00fa, de 6 a 9 de outubro. Sum\u00e1rio (apenas em ingl\u00eas): The need for executing complex Machine Learning (ML) algorithms, such as […]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/v2.joaomiguelvieira.com\/~joaovieira\/site\/pt\/2019\/06\/23\/artigo-aceite-na-conferencia-vlsi-soc19\/\" \/>\n<meta property=\"og:site_name\" content=\"Jo\u00e3o Vieira\" \/>\n<meta property=\"article:published_time\" content=\"2019-06-23T10:08:42+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2019-12-07T10:56:42+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/v2.joaomiguelvieira.com\/~joaovieira\/site\/wp-content\/uploads\/2019\/06\/machu_picchu-1.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1200\" \/>\n\t<meta property=\"og:image:height\" content=\"630\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"joaovieira\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"joaovieira\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/v2.joaomiguelvieira.com\/~joaovieira\/site\/pt\/2019\/06\/23\/artigo-aceite-na-conferencia-vlsi-soc19\/\",\"url\":\"https:\/\/v2.joaomiguelvieira.com\/~joaovieira\/site\/pt\/2019\/06\/23\/artigo-aceite-na-conferencia-vlsi-soc19\/\",\"name\":\"Artigo aceite na confer\u00eancia VLSI-SoC'19 - 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